Non-invasive Techniques Towards Recovering Highly Secure Unclonable Cryptographic Keys and Detecting Counterfeit Memory Chips

Due to the ubiquitous presence of memory components in all electronic computing systems, memory-based signatures are considered low-cost alternatives to generate unique device identifiers (IDs) and cryptographic keys. On the one hand, this unique device ID can potentially be used to identify major types of device counterfeitings such as remarked, overproduced, and cloned. On the other hand, memory-based cryptographic keys are commercially used in many cryptographic applications such as securing software IP, encrypting key vault, anchoring device root of trust, and device authentication for could services. As memory components generate this signature in runtime rather than storing them in memory, an attacker cannot clone/copy the signature and reuse them in malicious activity. However, to ensure the desired level of security, signatures generated from two different memory chips should be completely random and uncorrelated from each other. Traditionally, memory-based signatures are considered unique and uncorrelated due to the random variation in the manufacturing process. Unfortunately, in previous studies, many deterministic components of the manufacturing process, such as memory architecture, layout, systematic process variation, device package, are ignored. This dissertation shows that these deterministic factors can significantly correlate two memory signatures if those two memory chips share the same manufacturing resources (i.e., manufacturing facility, specification set, design file, etc.). We demonstrate that this signature correlation can be used to detect major counterfeit types in a non-invasive and low-cost manner. Furthermore, we use this signature correlation as side-channel information to attack memory-based cryptographic keys. We validate our contribution by collecting data from several commercially available off-the-shelf (COTS) memory chips/modules and considering different usage-case scenarios

DRAM Retention Behavior with Accelerated Aging in Commercial Chips

The cells in dynamic random access memory (DRAM) degrade over time as a result of aging, leading to poor performance and potential security vulnerabilities. With a globalized horizontal supply chain, aged counterfeit DRAMs could end up on the market, posing a significant threat if employed in critical infrastructure. In this work, we look at the retention behavior of commercial DRAM chips from real-time silicon measurements and investigate how the reliability of DRAM cells degrade with accelerated aging. We analyze the retention-based errors at three different aging points to observe the design-induced variations, analyze the pattern dependency, and explore the impacts of accelerated aging for multiple DRAM vendors. We also investigate the DRAM chips’ statistical distribution to attribute the vital wear-out effects present in DRAM. We see a continuous increase in retention error as DRAM chips age and therefore infer that the aged retention signatures can be used to differentiate recycled DRAM chips in the supply chain. We also discuss the roles of device signature in DRAM aging and aging-related security implication on DRAM row-hammer error

DRAM Retention Behavior with Accelerated Aging in Commercial Chips

The cells in dynamic random access memory (DRAM) degrade over time as a result of aging, leading to poor performance and potential security vulnerabilities. With a globalized horizontal supply chain, aged counterfeit DRAMs could end up on the market, posing a significant threat if employed in critical infrastructure. In this work, we look at the retention behavior of commercial DRAM chips from real-time silicon measurements and investigate how the reliability of DRAM cells degrade with accelerated aging. We analyze the retention-based errors at three different aging points to observe the design-induced variations, analyze the pattern dependency, and explore the impacts of accelerated aging for multiple DRAM vendors. We also investigate the DRAM chips’ statistical distribution to attribute the vital wear-out effects present in DRAM. We see a continuous increase in retention error as DRAM chips age and therefore infer that the aged retention signatures can be used to differentiate recycled DRAM chips in the supply chain. We also discuss the roles of device signature in DRAM aging and aging-related security implication on DRAM row-hammer error

Attacking Deep Learning AI Hardware with Universal Adversarial Perturbation

Universal adversarial perturbations are image-agnostic and model-independent noise that, when added to any image, can mislead the trained deep convolutional neural networks into the wrong prediction. Since these universal adversarial perturbations can seriously jeopardize the security and integrity of practical deep learning applications, the existing techniques use additional neural networks to detect the existence of these noises at the input image source. In this paper, we demonstrate an attack strategy that, when activated by rogue means (e.g., malware, trojan), can bypass these existing countermeasures by augmenting the adversarial noise at the AI hardware accelerator stage. We demonstrate the accelerator-level universal adversarial noise attack on several deep learning models using co-simulation of the software kernel of the Conv2D function and the Verilog RTL model of the hardware under the FuseSoC environment